A new version of Savage DRC system taps the full power of multiprocessor computers by introducing simultaneous execution of DRC commands from a DRC deck. A DRC deck is a set of DRC rules to be performed for a given layout. For typical DRC decks, the described approach alone delivers high processor utilization and speed-up. Further improvements are possible using parallelization by decomposition of IC layout data and exploiting its hierarchy.
Silvaco Data Systems announces the release of CELEBRITY CAD suite: Expert layout editor, Savage DRC system and Guardian LVS for Linux platform.
It is well-known that parasitic effects are no longer negligible for modern integrated circuit technology. Among the most important parasitic effects limiting the chip performance are interconnect related problems like extensive signal delays and crosstalk. The main numeric problem is extraction of parasitic capacitance, because it is a more complicated task than resistance extraction. The latest codes use directly 3D electrostatic solvers for this purpose. But the disadvantage of such approach is prohibitively long solution time for the problem. So the simplest model of 3D structures, when layout is splitted to 2D small pieces, can be used when it is necessary to handle complete IC's in a reasonable amount of time.
To provide uniform etching of metal, dummy metal rectangles can be placed over an unused area of the chip. The following script generates dummy layer with a full array of metal rectangles over the whole cell area. It calls DRC script
Q: How can I cut exactly the same hole in many layers? Q: How to skip a single layer during stream-out? Q: How to do filler boxes in Expert?
In this contribution we present a model for transient enhanced diffusion of boron in silicon. This model is based on the usual pair diffusion mechanism including non-equilibrium reactions between the dopant and the free point defects, taking into account their various charge states. In addition to, and fully coupled with the dopant diffusion we model the growth and dissolution of the interstitials and boron interstitials clusters associated with the anneal of the self-interstitial supersaturation created by the implantation step. It is thus possible to simulate a rather large set of experimental conditions, from conventional predeposition steps, to RTA after low energy implantation.
Interest continues to grow in the development of high electron mobility transistor (HEMT) technologies for micrometer and millimeter wave power applications. A primary concern of device designers working with such technologies is the breakdown behavior in both the on- and off-states. As is the case for most field-effect transistors, reducing device dimensions results in a larger internal electric field near the drain-end of the device?s channel. The presence of such a field within the device can affect many areas of device performance including the breakdown characteristics.
This article presents a standard case of transmission line: the microstrip structure. First, the structure is described and then the results extracted from QUEST are compared with measurements. We thank STMicroelectronics (Crolles-R&D) for experimental data support.
ATLAS allows the user to define a contact with a number of different boundary conditions; ohmic, Schottky, current controlled, floating or reflecting. The Schottky contact boundary condition realizes that at the metal semiconductor interface a barrier exists due to the presence of interface states.
We give in this article an introduction to the Verilog-A SmartSpice interface. This new feature in SmartSpice allows the user to write their own physical models in the Verilog-A language. The first section of the paper gives a brief overview of the Verilog-A language. The second presents the ease of use of simulating transistor models as well as digital circuits with the new Verilog-A SmartSpice interface.