Simulation Standard

Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]–[3]. The development of vertical devices, like pn-diodes and power HEMTs results in higher power density and voltage handling. One of the key parameters of this technology is the dislocation density. This is lower in free-standing GaN-on-GaN epitaxy than in heteroepitaxial GaN growth on different substrates like SiC or Si, but still has a density of 104-106 cm-2 [4]. The diode reverse leakage seems to be related to the dislocation density, and it can be modelled with a Poole-Frenkel or a hopping conduction mechanism [5]. The Poole-Frenkel model is already implemented in the trap-assisted tunnelling model in Silvaco Atlas [6]. For the leakage in threading dislocations a variable-range hopping (VRH) model has been implemented in the simulator, based on Ref. [7].

This document describes how to setup a virtual environment suitable for the deckbuild remote mode. The host system to consider shall be Windows (7 or 10). The goal is to use the windows version of the TCAD GUI tools TonyPlot and DeckBuild and to run any simulation (Victory, Athena, Clever) on a Linux Virtual Machine (VM).

Cryogenic electronics plays a fundamental role in several applications, such as spacecraft, high-energy physics experiments, metrology, superconductive astronomical detectors and, with the increased interest in quantum computing, the manipulation of quantum bits (qubits) [1]. Outstanding characteristics have been reported for advanced CMOS technologies operating at cryogenic temperature in terms of on-state current, leakage current, subthreshold swing, and transconductance [2]. This represents an excellent opportunity to use such advanced technologies to design and implement a quantum computing control system (including multiplexers, LNAs, and RF oscillators) and introduce it inside the refrigerator together with the qubits [3]. Another recently growing field of application is the cryogenic silicon photonics [4].

For high performance large area flexible electronics, amorphous metal oxide semiconductor based thin film transistors offer many advantages. These include high mobility, steep sub-threshold and ultralow leakage current, with low cost and large area manufacturability.

Gallium Nitride High Electron Mobility (GaN HEMT) device technology has gained a lot of traction during the last years. These devices have significant advantages compared to Silicon in user applications such as high frequency/high power amplifiers, radar systems, power conversion and applications where stability over a wide range of temperatures is required, such as automotive-related.

Geometrical module of Victory Process allows the fast and accurate transfer of mask patterns to the structure. However, sometimes it is necessary to emulate the imperfections of physical processes while retaining the speed and accuracy of the geometrical approximation. For example, you may want to test the tolerance of the final device to random fluctuations in structure’s geometry.

Lower conduction loss and fast switching characteristics for power devices are increasingly required in the more and more energy-conscious world. For the low to medium voltage ranges (12 V ~ 250 V), the split gate structures [1] have become prevalent in the power MOSFET technologies [2-4]. They allow to achieve the best trade-off between the breakdown voltage (BV) and specific on-state resistance (RSP) for the vertical discrete power MOSFETs. Most of these solutions are based on the RESURF (Reduced Surface Field) action of Split-Gate Resurf Stepped Oxide (SG-RSO) along the drift region.

It is often the case, that an Engineer is required to simulate environmental effects on a device manufactured by a third party.  In such an event, the first issue that is faced by the Engineer, is a lack of access to the manufacturing process that created the third party device in the first place.  In this article, it is shown how to overcome this first issue, and reverse engineer a sufficiently representative base device, simply from the manufacturer’s specification sheet.  Once a satisfactory device has been fabricated, it can be used in the required simulation to analyze any effects of interest.  In this particular case, we will demonstrate the damaging effects of irradiating a 2N2222A bipolar transistor with a proton flux and compare the simulated results with other similar measured results.

In recent years, radio-frequency (RF) CMOS on Silicon-on-Insulator (SOI) has rapidly evolved as a mainstream technology for switches used in wireless applications such as tuners and power amplifiers [1, 2]. Since such applications can involve switching high power levels at high frequencies (~2 GHz), the technology considerations are substantially different than those for SOI used in high speed, small signal applications such as microprocessors. Requirements of lower insertion loss, better isolation, and better linearity have driven RF CMOS-SOI roadmap.

In connection with the reduction in the size of electronic elements and the increase in operating frequencies, it becomes necessary to transmit signals between the nodes of the circuit using micro strip transmission lines. . Micro strip is similar to strip line transmission line except that the micro strip is not sandwiched, it is on a surface layer, above a ground plane. A strip line circuit uses a flat strip of metal which is sandwiched between two parallel ground planes. The insulating material of the substrate forms a dielectric. The width of the strip, the thickness of the substrate and the relative permittivity of the substrate determine the characteristic impedance of the strip which is a transmission line. As shown in the diagram, the central conductor need not be equally spaced between the ground planes. In the general case, the dielectric material may be different above and below the central conductor.