\nToday\u2019s foundries offer a wide variety of process nodes ranging in size from 250nm, and above, down to 7nm and below. Process nodes of 110nm, and above, are considered mature since they have been in the market for over 20 years.<\/p>\n
![\"\"](\"\/wp-content\/uploads\/2020\/04\/blog42-223x300.png\")
<\/figure>\n<\/div>\nThe standard cell libraries that were developed earlier at that time do not include recent technology developments. Here is a list of how standard cells and process offerings have changed over this time:<\/p>\n
- \n
- Tapless architecture<\/li>\n
- Clock gating<\/li>\n
- Vt variants.<\/li>\n
- Power management kits (PMK) & multi-power islands<\/li>\n
- Multi-bit FFs<\/li>\n
- Fine grain sizing<\/li>\n
- Complex function matching<\/li>\n<\/ul>\n
This means that legacy libraries can be further improved for power footprint, performance and area.<\/p>\n
With 700 \u2013 1,200 standard cells and multi VTs\u00a0 and track heights, the Silvaco standard library offers thousands of cell variants, enabling applications from ultra-low power to high-speed. Silvaco carefully sizes each cell family in the library, optimizing transistor sizes, P\/N ratios and drive strength granularity for further power and performance gains. Silvaco\u2019s EDA platform for Layout Optimization, Cello, enables a new level of optimization, with 35% area and 20% power reduction compared to off-the-shelf libraries from other vendors. Multi-bit and multi-height standard cells boost routing density even further by reducing pin count and packing more functionality inside standard cells. For instance the detailed review and exploration of 180nm design rules by Silvaco engineers resulted in the creation of a cell architecture that achieves a raw gate density of 162K gates per square millimeter.<\/p>\n
The Silvaco library is extended with a Power Management Kit, taking power reduction to the next level with features such as multi-voltage design and power gating. Libraries are characterized for multiple PVT corners with extended voltage range and are compatible with multiple foundries.<\/p>\n
To use a Silvaco Foundation library in your next project, you can contact Silvaco or you can request it from your Foundry.\u00a0 Many foundries already have our optimized library even if they are not listed.<\/p>\n
Summary<\/strong><\/p>\n
![\"\"](\"\/wp-content\/uploads\/2020\/04\/blog45-206x300.png\")
This has been a quick tour of the available Foundation IP from Silvaco. Our standard cell libraries support multiple Foundries, multi-Vt, multi-bit FFs and come with come with standard and custom PVT corners. For each library, add-ons include Power management kits (PMKs) and ECO Kits with fixed pattern for FEOL layers. Through our platform Cello we offer library creation, migration and optimization services down to 7nm process nodes.\u00a0 To find out more about our custom services or our ready-to-go Foundation IP:
\n\u00ba\u00a0 6\/7\/9\/10\/12 track libraries for the 180\/152nm, 130\/110nm, 90\/80nm, 65\/55nm process nodes
\n\u00ba\u00a0 7\/8\/9\/10\/12 track libraries for the 40nm and 28\/22nm nodes<\/p>\n