{"id":31016,"date":"2007-02-01T00:04:44","date_gmt":"2007-02-01T00:04:44","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/how-can-i-significantly-reduce-circuit-parasitics-netlist-extraction-time\/"},"modified":"2021-07-16T21:46:47","modified_gmt":"2021-07-17T04:46:47","slug":"how-can-i-significantly-reduce-circuit-parasitics-netlist-extraction-time","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/simulation-standard-ko\/how-can-i-significantly-reduce-circuit-parasitics-netlist-extraction-time\/","title":{"rendered":"How Can I significantly Reduce Circuit Parasitics Netlist Extraction Time?"},"content":{"rendered":"
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Hints, Tips and Solutions – February 2007<\/h1>\n

Q.\u00a0<\/strong>How Can I significantly Reduce Circuit Parasitics Netlist Extraction Time?<\/p>\n

A.<\/strong>\u00a0SILVACO has recently released a new suite of parasitic extraction tools to meet the demands of state-of-the-art designers at cell, circuit and chip level. After having proved [1] [2] [3] the accuracy of these tools, SILVACO now focuses his attention to decrease the simulation time, by taking benefit from Multi-CPUs computing architectures.<\/p>\n

The results presented here have been obtained with\u00a0STELLAR<\/em><\/strong>, a 3D-based Field Solver with full-chip capacitance extractor. The software uses an advanced numerical method, the so-called fictitious domain method, which is based on the decomposition of the simulation domain into sub-domains. The parallel version of\u00a0STELLAR<\/em><\/strong>\u00a0accepts a command line option -P n, which allows running the m sub-domains simulations in parallel on n CPUs (n being the number of requested CPUs). Simulations were done by STMicroelectronics Crolles France on a SunOS 5.8, 16 CPUs, Sun-Fire-V890. The layout used for this study had the following characteristics: 106×230 um2<\/sup>\u00a0area, 7 metal layers and 6 via layers. In the following text and figures, the CPU time is the total on-CPU time as measured by a UNIX ps or top command, while the Wallclock time is the real-world time, as measured by a watch.<\/p>\n

The decomposition algorithm is sufficiently robust to give a very limited (3%) variation of the capacitance with the number of sub-domains represented by a decomposition step d (Figure 1). High value of d correspond to a low number of sub-domains. It is also clear from Figure 1 that CPU time increases with d. As a consequence it was decided to set d to 1.91 corresponding to 90 sub-domains. It has been verified that for a given decomposition, the capacitance does not vary with the number of requested CPUs.<\/p>\n

As can be seen in Figure 2, the parallelization is very good (near the theoretical limit) for a number of requested CPUs around 8. Running on 12 CPUs leads to a gain time of a factor 9. The layout used for this benchmark was relatively small. The advantage of parallelization over a larger number of CPUs maybe even more advantageous for larger structures. This result is achieved easily (no preliminary optimization runs) if the decomposition step d is chosen such that a large number of subdomains is obtained (90 in this case). In other words the parallelization is fully exploited only if n is significantly lower than m.<\/p>\n<\/div><\/section><\/div>

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