{"id":31025,"date":"2006-11-01T00:03:47","date_gmt":"2006-11-01T00:03:47","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/design-rules-and-trends-for-dummy-metal-filling-using-exact-clever-and-stellar\/"},"modified":"2021-07-16T21:47:02","modified_gmt":"2021-07-17T04:47:02","slug":"design-rules-and-trends-for-dummy-metal-filling-using-exact-clever-and-stellar","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/design-rules-and-trends-for-dummy-metal-filling-using-exact-clever-and-stellar\/","title":{"rendered":"Design Rules and Trends for Dummy Metal Filling Using Exact, Clever and Stellar"},"content":{"rendered":"

Design Rules and Trends for Dummy Metal Filling Using Exact, Clever and Stellar<\/h1>\n

Introduction<\/h3>\n

The physical verification is becoming the most complex phase raised by the Deep SubMicron (DSM) technology. More than 50% of the design time is dedicated to the verification. With the shrink of transistors size, the interconnect delay is dominant versus gate delay. Hence the challenge in the DSM technology depends primarily on how to provide accurate characterization of these interconnects. This is especially the case when dummy metals are present.<\/p>\n

Floating dummy metals which are inserted to assist planarization of multi-dielectric layers by chemical-mechanical polishing (CMP) process, have created serious problems because of increased interconnect capacitance. We study in this article dummy filling methods to reduce the interconnect capacitance. These techniques include three ways of filling: 1) square 2) parallel lines, and 3) perpendicular lines. For that purpose, we use parameterized layouts allowing, very easily, the variation of dummies geometrical parameters. We then calculate capacitance by using two types of field solver described below. Finally a capacitance model, depending on the dummies geometry is created in order to perform the optimization of the dummies geometry and number.<\/p>\n

Parameterized Layout<\/h3>\n

For this study, we consider a very simple layout consisting of a line over a ground plane surrounded by dummy metals. We wanted to study the impact of dummies geometry and their number on the capacitance between the line and the substrate. For that we use a parameterized layout generator including in our\u00a0EXACT<\/em><\/strong>\u00a0[1] tool.<\/p>\n

The parameterized structure layout generator, within\u00a0EXACT<\/em><\/strong>, provides the user with the capability to define their test structures. This is what was done in this experiment. One combines graphical user interface of\u00a0EXACT<\/em><\/strong>\u00a0with proprietary scripting language\u00a0LISA<\/em><\/strong>\u00a0from SILVACO. All the variables are defined within the GUI as shown in Figure 1 as long as a part of the layout. The dummies are defined using the scripting language\u00a0LISA<\/em><\/strong>\u00a0as shown in Figure 2. It generates one column of dummies at a fixed x-ordinate. In this study, 4 columns have been defined. Therefore this piece of script appended to the layout file saved by the GUI of\u00a0EXACT<\/em><\/strong>.<\/p>\n

\"\"<\/p>\n","protected":false},"excerpt":{"rendered":"

Introduction<\/p>\n

The physical verification is becoming the most complex phase raised by the Deep SubMicron (DSM) technology. More than 50% of the design time is dedicated to the verification. With the shrink of transistors size, the interconnect delay is dominant versus gate delay. Hence the challenge in the DSM technology depends primarily on how to provide accurate characterization of these interconnects. This is especially the case when dummy metals are present.<\/p>\n","protected":false},"author":3,"featured_media":22353,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7486],"tags":[],"class_list":["post-31025","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard-ko","entry","has-media"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31025","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/comments?post=31025"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31025\/revisions"}],"predecessor-version":[{"id":31030,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31025\/revisions\/31030"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/media\/22353"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/media?parent=31025"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/categories?post=31025"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/tags?post=31025"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}