{"id":31117,"date":"2004-10-01T00:04:17","date_gmt":"2004-10-01T00:04:17","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/a-sophisticated-verilog-a-debugger\/"},"modified":"2021-07-16T21:51:30","modified_gmt":"2021-07-17T04:51:30","slug":"a-sophisticated-verilog-a-debugger","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/a-sophisticated-verilog-a-debugger\/","title":{"rendered":"A Sophisticated Verilog-A Debugger"},"content":{"rendered":"<h1>A Sophisticated Verilog-A Debugger<\/h1>\n<p>During the elaboration of a\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0debugger has been designed to meet these needs. It is available since version 2.6.0.R of\u00a0<strong><em>SmartSpice<\/em><\/strong>\u00a0and works along with SILVACO C-Interpreter. It allows iteration-per-iteration\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0modules debugging. The debugger is tracing all the\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0instantiations of the design, either instances of the\u00a0<strong><em>SmartSpice<\/em><\/strong>\u00a0netlist or in other\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0modules.<\/p>\n<p>The BSIM4\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0model (bsim4.va) and the adder design (adder.in) used as an example are freely available on SILVACO website.<\/p>\n<p>It can be enabled by setting in the input deck:<\/p>\n<blockquote><p><span style=\"font-family: Courier New, Courier, mono;\">.OPTIONS va_mode=debug<\/span><\/p><\/blockquote>\n<p>The debugger appears when the simulation of this input deck is launched. The simulation stops at the first instruction (a breakpoint at the first instruction is always set by default). In the case of BSIM4 model, the first instruction encountered is the initial_step event in the analog block. The layout of the main window at startup<\/p>\n<p>The\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0source code is displayed in an editor window. Syntax highlighting is available and its colors are fully customizable. Line numbers can be displayed by checking the \u201cShow line number\u201d box in the Properties dialog window (Edit &gt; Properties&#8230;).<\/p>\n<p>The console window is at the bottom of the main window. The error messages are printed in this area and the user can enter commands manually.<\/p>\n<p>In this example (Figure 2. The console window), a breakpoint has been set at line 2699 (the end of the initial_step block) and the simulation has been started with the cont command. The edit window has now the aspect.<\/p>\n<p><img loading=\"lazy\" width=\"644\" height=\"800\" src=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_oct_2004_a3-e1611193421702.jpg\" class=\"cleaned-enfold-image\" alt=\"\" decoding=\"async\" loading=\"lazy\" \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>During the elaboration of a\u00a0Verilog-A\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO\u00a0Verilog-A\u00a0debugger has been designed to meet these needs. It is available since version 2.6.0.R of\u00a0SmartSpice\u00a0and works along with SILVACO C-Interpreter. It allows iteration-per-iteration\u00a0Verilog-A\u00a0modules debugging. The debugger is tracing all the\u00a0Verilog-A\u00a0instantiations of the design, either instances of the\u00a0SmartSpice\u00a0netlist or in other\u00a0Verilog-A\u00a0modules.<\/p>\n","protected":false},"author":3,"featured_media":22551,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7486],"tags":[],"class_list":["post-31117","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard-ko","entry","has-media"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31117","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/comments?post=31117"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31117\/revisions"}],"predecessor-version":[{"id":31122,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31117\/revisions\/31122"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/media\/22551"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/media?parent=31117"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/categories?post=31117"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/tags?post=31117"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}