www.ieee.org<\/a>.<\/p>\nKeh-Jeng Chang, Jyh-Jeng Chou, Hung-Chih Li, and Kuo-Cheng Chang,
\n“Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM”,
\nInternational Symposium on VLSI Design, Automation and Test, 2008. VLSI- DAT 2008. IEEE, April 2008, pp. 291 – 294.<\/p>\n
C. Xu, R. Gharpurey, T. S. Fiez, K. Mayaram,
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A.K. Goel, and H. Gopinathannair,
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C. Renard (SILVACO Data Systems), P. Scheiblin, F. De Crecy, A. Ferron, E. Guichard, P. Holliger, C. Laviron,
\n“Methodology for prediction of ultra shallow junction resistivities considering uncertainties with a genetic algorithm optimization”
\n2004 NSTI Nanotechnology Conference and Trade Show – NSTI Nanotech 2004, Vol. 2, 2004 NSTI Nanote.<\/p>\n
D. Lederer, J. -P. Raskin,
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Sheehan DP, Putnam AR, Wright JH,
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\nSchoellkopf, and H. Jaouen,
\n“New interconnect capacitance characterization method for multilevel metal CMOS processes”
\nIEEE International Conference on Interconnect Technology, 1999, pp. 224 – 226.<\/p>\n
S. Putot, F. Charlet, and P. Witomski,
\n“A fast and accurate computation of interconnect capacitance”
\nInternational Electron Device Meeting, Dec. 1999, pp. 893-896.<\/p>\n
D. Salameh and D. Linton,
\n“Study of the effect of various parameters on nonlinear transmission-line (NLTL) performance”
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Tan, Jilin and Pan, Guang-Wen,
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\nIEEE Transactions on Components, Packaging & Manufacturing Technology, Part B, August 1996, Vol. 19 Issue 3. pp. 621-627.<\/p>\n","protected":false},"excerpt":{"rendered":"
Interconnect Simulation The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Keh-Jeng Chang, Jyh-Jeng Chou, Hung-Chih Li, and Kuo-Cheng Chang, “Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM”, International Symposium on VLSI Design, Automation and Test, 2008. VLSI- DAT 2008. IEEE, April 2008, […]<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7663,7655],"tags":[],"class_list":["post-31711","post","type-post","status-publish","format-standard","hentry","category-interconnect-simulation-ko","category-tcad-published-papers-ko","entry"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31711","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/comments?post=31711"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31711\/revisions"}],"predecessor-version":[{"id":39169,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/posts\/31711\/revisions\/39169"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/media?parent=31711"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/categories?post=31711"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/wp-json\/wp\/v2\/tags?post=31711"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}