{"id":65600,"date":"2026-05-29T12:07:50","date_gmt":"2026-05-29T19:07:50","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/silvaco-at-dac-2026\/"},"modified":"2026-07-01T09:59:18","modified_gmt":"2026-07-01T16:59:18","slug":"silvaco-at-dac-2026","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/ko\/silvaco-at-dac-2026\/","title":{"rendered":"Silvaco at DAC 2026"},"content":{"rendered":"

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Join Silvaco at DAC 2026<\/h1>\n

July 26 \u2013 July 29, 2026
\nLong Beach Convention Center | Booth 1155<\/h4>\n

Join us at DAC where innovation in semiconductor design comes to life. Stop by our booth to explore how we are advancing AI-driven design, modeling, and IP solutions.<\/p>\n

Featured Technologies<\/strong><\/h1>\n

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Utmost \u2014 AI-Driven SPICE Model Extraction & Characterization
\n<\/strong>Generate accurate, design-ready compact models in a fraction of the time.
\nUtmost transforms process and device data into SPICE models your simulations can trust\u2014ensuring alignment between simulation and silicon while reducing manual tuning, model uncertainty, and costly respins.<\/p>\n

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Jivaro \/ Viso \u2014 AI-Driven Parasitic & Analog Analysis
\n<\/strong>Eliminate post-layout surprises in analog and mixed-signal design.
\nJivaro and Viso apply machine learning to parasitic extraction and analysis, helping identify yield-impacting effects early and closing the gap between pre- and post-layout simulation.<\/p>\n

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CellForge \u2014 Standard Cell Library Automation
\n<\/strong>From transistor netlist to DRC-clean layout \u2014 faster.
\nCellForge 3D automates standard cell layout generation for advanced-nodes, helping teams reduce manual effort and focus on design optimization.<\/p>\n

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Silvaco Memory IP
\n<\/strong>Accelerate time-to-market with silicon-proven memory solutions.
\nSilvaco PRO Memory IP delivers SP-SRAM, DP-SRAM, register files, and ROM across nodes from 130nm to 22nm\u2014enabling rapid integration and meeting the accelerated product cycles driven by AI innovation.<\/p>\n

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Mixel MIPI IP
\n<\/strong>Power high-performance data interfaces for AI-driven systems.
\nSilvaco\u2019s Mixel MIPI IP portfolio is silicon-proven across 9 foundries and 12 process nodes (180nm to 5nm), enabling efficient sensor-to-system data transfer for applications including automotive, wearable, and robotics.<\/p>\n

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IPGrid (IPAudit\/IPVault)
\n<\/strong>Track all your IP in a centralized location and improve traceability and reuse across teams, sites, and programs.<\/p>\n

Featured Speaking Session<\/h1>\n

Join Silvaco CEO Wally Rhines at Cooley\u2019s DAC Troublemaker Panel\u2014a candid, open Q&A addressing the most pressing and controversial topics in EDA today.<\/p>\n

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View Session Details<\/a><\/p>\n

Schedule a Meeting<\/h1>\n

Connect with our experts to discuss your design challenges and discover how Silvaco can support your next breakthrough.
\n? Email: sales@silvaco.com<\/a><\/p>\n

Your Free Pass to DAC 2026 is Waiting<\/h1>\n

Get your FREE \u201cI Love DAC\u201d pass until July 12, 2026<\/p>\n