Silvaco SmartSpice 2021 – Top 10 New Features in the Baseline Release
August 19, 2021 | 10:00 am – 10:30 am (PDT) In this webinar, we present the top 10 new features and improvements enabled by the SmartSpice team during this past year.
How to Model and Simulate Flat Panel Pixel Arrays
May 13, 2021 | 10:00 am – 10:35 am (PDT) In this webinar we will look at some of the effects to check when designing a flat panel.
How to Accelerate Post-layout Parasitics Analysis and Avoid Wasted Simulation Cycles
April 20, 2021 | 10:00 am – 10:30 am (PDT) In this webinar we will show how to accelerate post-layout parasitics analysis and avoid wasted simulation cycles
Learn How Silvaco’s SmartSpice is Getting Faster
March 4, 2021 | 10:00 am – 10:20 am (PST) In this Webinar, we present (1) a general overview of SmartSpice, our SPICE simulation tool; (2) what is new on SmartSpice 4.44.3.R, our latest yearly release; and (3) a brief introduction of what can be expected for our next yearly release.
How to Quickly Achieve Accurate SPICE Models with Utmost IV
March 16, 2021 | 10:00 am – 10:20 am (PST) This webinar will review the various Silvaco SPICE modeling solutions. This includes a brief overview of our tools, Utmost IV and TechModeler, and of the modeling services that we provide to our customers. We discuss a few of our recent modeling examples for various technologies, including display-related, RF SPICE modeling, and advanced processes.
Good News – The Silvaco Analog Custom Design Flow
December 17, 2020 | 10:00 am – 10:15 am (PST) In this webinar, we describe Silvaco’s Analog Custom Design solution and how the 2020 release addresses the driving forces of better interoperability, performance, and productivity.
Customer Interview: Why I Rely on SmartSpice
Martin Mallinson is an experienced analog circuit designer with multiple patents. Over his 40-year career, his audio designs have been used in millions of smartphones. Martin spoke with Graham Bell about why SmartSpice is different from other analog simulators and how he relies on its interactivity, speed, and precision for his analog design work.
Simulate 40X Faster with SmartSpice HPP
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
Using SmartSpice Compact Models
June 11, 2020 | 10:00 am – 10:30 am (PDT) This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn how models are used in SmartSpice and best practices when constructing a custom Verilog-A model.