{"id":35388,"date":"2021-08-17T09:06:28","date_gmt":"2021-08-17T16:06:28","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/designing-with-silvaco-octal-spi-memory-controller-with-advanced-memory-support-for-iot-systems\/"},"modified":"2021-10-20T23:32:27","modified_gmt":"2021-10-21T06:32:27","slug":"designing-with-silvaco-octal-spi-memory-controller-with-advanced-memory-support-for-iot-systems","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/designing-with-silvaco-octal-spi-memory-controller-with-advanced-memory-support-for-iot-systems\/","title":{"rendered":"Designing with Silvaco&#8217;s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems"},"content":{"rendered":"<p><img loading=\"lazy\" width=\"1920\" height=\"201\" src=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" class=\"cleaned-enfold-image\" alt=\"Banner Blue\" decoding=\"async\" loading=\"lazy\" srcset=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" sizes=\"auto, (max-width: 1920px) 100vw, 1920px\" \/><\/p>\n<h1 class=\"p1\"><span class=\"s1\">Designing with Silvaco&#8217;s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems<\/span><\/h1>\n<p class=\"p1\">One commonality across semiconductor market segments is the need for memory.\u00a0\u00a0However, memory characteristics and interfaces vary greatly depending on the market segment and application.\u00a0This webinar will focus on a specific class of memory devices \u2013 targeted to mobile and IoT applications \u2013 that use \u201cSPI\u201d (Serial Peripheral Interface) signaling.<\/p>\n<p class=\"p1\">SPI was developed by Motorola in 1979 for short-distance communication within embedded systems.\u00a0Its popularity grew quickly, and SPI soon spawned many variants but lacked a unifying standard.\u00a0Almost 30 years after its inception, SPI was adopted by FLASH memory manufacturers to satisfy growing demand in the emerging IoT space.\u00a0As edge devices became more complex, a push for greater memory performance resulted, and the SPI interface evolved to meet these new challenges: Dual, Quad, Octal and Octal DDR (Double Data Rate) SPI variants ensued.\u00a0With Octal DDR, the performance of the interface was sufficient to support RAM devices in addition to FLASH devices, some much-needed standardization was realized in the form of several similar, overlapping specifications.<\/p>\n<p class=\"p1\">Today\u2019s IoT systems need a solution for interfacing with these memories: the Octal SPI Memory Controller.<span class=\"Apple-converted-space\">\u00a0 <\/span>This product from Silvaco contains powerful features such as XIP (Execute In Place) and supports FLASH and PSRAM memories.<\/p>\n<p class=\"p1\"><b>What You Will Learn<\/b><\/p>\n<ul>\n<li>Octal SPI Controller architecture and key features<\/li>\n<li>Implementation of a typical Octal SPI integration in an embedded system<\/li>\n<li>Operating modes will be defined and explained<\/li>\n<li>Seamless memory access, support for a range of memory devices, and flexibility to accommodate various clocking and integration scenarios<\/li>\n<li>XIP (Execute in Place) and PSRAM support<\/li>\n<\/ul>\n<h2>Presenter<\/h2>\n<p><img decoding=\"async\" class=\"wp-image-34005 alignleft\" src=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2021\/08\/Errett_headshot.jpg\" alt=\"Errett_headshot\" width=\"84\" height=\"106\" srcset=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2021\/08\/Errett_headshot.jpg 203w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2021\/08\/Errett_headshot-29x37.jpg 29w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2021\/08\/Errett_headshot-44x55.jpg 44w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/2021\/08\/Errett_headshot-38x48.jpg 38w\" sizes=\"(max-width: 84px) 100vw, 84px\" \/><\/p>\n<p class=\"p1\">Errett Hogrefe is a Senior Digital Design Engineer in Silvaco&#8217;s IP Division.<span class=\"Apple-converted-space\">\u00a0 <\/span>Errett is the architect, developer, and supporter of many digital cores in Silvaco&#8217;s IP portfolio, including SPI, Quad-SPI and Octal-SPI Controllers. Errett joined Silvaco in 2017 and prior to joining Silvaco Errett was an engineer of various descriptions for 16 years at SoC Solutions.<\/p>\n<h3>WHO SHOULD ATTEND:<\/h3>\n<p class=\"p1\">IP, Circuit, CAD, SoC and System design engineers, product managers and engineering management.<\/p>\n<p><strong>When<\/strong>: September 9, 2021<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-10:30am-(PDT)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<div style=\"padding: 10px; background-color: #99ccff;\">\n<h1 align=\"center\">Register<!-- to view On-Demand Webinar-->!<\/h1>\n<p><iframe style=\"border: 0;\" src=\"https:\/\/go.silvaco.com\/l\/145371\/2021-08-16\/2zgbyp\" width=\"100%\" height=\"500\" frameborder=\"0\"><\/iframe><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p><b>September 9, 2021 | 10:00 am \u2013 10:30 am (PDT)<\/b><br \/>\nThis webinar will focus on a specific class of memory devices \u2013 targeted to mobile and IoT applications \u2013 that use \u201cSPI\u201d (Serial Peripheral Interface) signaling.<\/p>\n","protected":false},"author":8,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7726],"tags":[],"class_list":["post-35388","post","type-post","status-publish","format-standard","hentry","category-sipware-webinars-zh-hans","entry"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/35388","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/users\/8"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/comments?post=35388"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/35388\/revisions"}],"predecessor-version":[{"id":35391,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/35388\/revisions\/35391"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media?parent=35388"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/categories?post=35388"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/tags?post=35388"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}