{"id":35499,"date":"2020-12-14T16:06:53","date_gmt":"2020-12-15T00:06:53","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/reducing-the-layout-development-cycle-time-for-standard-cells\/"},"modified":"2021-09-22T13:46:43","modified_gmt":"2021-09-22T20:46:43","slug":"reducing-the-layout-development-cycle-time-for-standard-cells","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/reducing-the-layout-development-cycle-time-for-standard-cells\/","title":{"rendered":"Reducing the Layout Development Cycle Time for Standard Cells"},"content":{"rendered":"

\"Banner<\/p>\n

Reducing the Layout Development Cycle Time for Standard Cells at STMicroelectronics<\/h1>\n

As the semiconductor industry is evolving, product turnaround time must be reduced while ensuring high quality, reliability, and profitability. This requirement translates to the reduction of standard cell layout development cycle time without compromising robustness, density, and manufacturability of the integrated circuits that are produced.<\/p>\n

The presenters introduce the Cello platform for creating and optimizing standard cell libraries. It includes a layout optimization engine, a built-in Tcl interpreter with a scripting API, distributed jobs support, and export of backend views. Starting from layout creation from the schematic, it can ease the designer\u2019s life for improvement, migration, and validation of cell layouts. These features are easily integrable inside the conventional layout development framework and enable layout engineers to design standard cell layouts faster.<\/p>\n

In this webinar, Sharmistha Sinha and Anand Mishra share their analysis and experience with Cello done at ST on multiple technologies. Based on this study, they identified the scope to improve the overall efficiency of standard cell development. The results showed effort savings of approximately 40% by using Cello for the development of layouts from start to finish.<\/p>\n

Presenter<\/h2>\n

\"\"<\/p>\n

Sharmistha Sinha
\nSr. Design Engineer, STMicroelectronics<\/p>\n

Sharmistha Sinha is a Senior Design Engineer at ST Microelectronics. She has five years of experience in the Standard Cell domain in the semiconductor industry. She has been working with STM for three years. She worked with NXP and Maxim before joining STM. She has a master\u2019s degree in VLSI from Amity University, Noida.<\/p>\n

\"\"Anand Kumar Mishra
\nSr. Manager, STMicroelectronics<\/p>\n

He is currently serving as senior manager in the Standard Cell development team at ST Microelectronics PVT Ltd Noida. Anand Kumar Mishra graduated from Institute of technology Banaras Hindu University (now IIT-BHU) in 2001. He worked for SRAM development in ST for 16 years before joining standard cell development team. His topics of interest are high density SRAM, standard cell for low power applications, and process monitoring structures.<\/p>\n

WHO SHOULD ATTEND:<\/h3>\n

Design and verification engineers and managers looking for solutions to increase efficiency and accuracy while reducing time and costs of standard cell library creation, migration, and optimization.<\/p>\n

When<\/strong>: January 14, 2021
\nWhere<\/strong>: Online
\nTime<\/strong>: 10:00am-10:20am-(PST)
\nLanguage<\/strong>: English<\/p>\n

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Register!<\/h1>\n