{"id":35544,"date":"2020-09-03T20:58:19","date_gmt":"2020-09-03T20:58:19","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/"},"modified":"2021-09-22T13:50:58","modified_gmt":"2021-09-22T20:50:58","slug":"choosing-the-right-ddr-memory-subsystem-for-your-next-soc","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/","title":{"rendered":"Choosing the Right DDR Memory Subsystem for Your Next SOC!"},"content":{"rendered":"

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Choosing the Right DDR Memory Subsystem for Your Next SoC!<\/h1>\n

As computational requirements continue to grow and memory systems are operating at even higher frequencies, the demand for high-performance memory subsystems that are more dense, consume less power, and occupy smaller silicon continues to grow rapidly across key application segments such as high-performance computing platforms, 5G, Automotive, and IoT applications.<\/p>\n

In this webinar, we will introduce Samsung Foundry PHY IP offerings with its unique technology, OpenEdges\u2019s multi-protocol controller, and Silvaco\u2019s subsystem IP. Attendees will learn how to achieve plug-and-play solutions for DDR memory subsystem in new SoC designs. Both technology features and complementary services to help design efficient memory subsystems will be included in the presentation.<\/p>\n

To view our webinar register to view content.<\/h3>\n

Presenter<\/h2>\n

\"Kwanyeob<\/p>\n

Kwanyeob Chae is a Principal Engineer at Samsung Foundry and responsible for DDR PHY design in IP development team. He is engaged in the development of digital circuits and design methodologies for high speed memory interface. His research interests include design methodology, physical implementation, high speed digital PHY architecture, self-adaptive circuits, low-power circuits, and variation-tolerant design. Kwanyeob Chae received his B.S. and M.S. degrees in electronics engineering from Korea University, Seoul, Korea. He received his Ph.D. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta.<\/p>\n

\"SeanSean Lee is CEO of Openedges Technology, Inc. and responsible for managing strategic growth of the company through technological leadership. He has more than 20 years of IP and SoC design experiences including numerous generations of Exynos mobile AP for Galaxy Smartphones. His background includes CPU architecture, memory subsystem IP design, and mobile AP SoC design, and he holds several patents on memory subsystem architecture. Sean holds B.S. and M.S. degree in Electrical Engineering and Computer Science from Seoul National University of South Korea.<\/p>\n

\"AshishAshish Shrotriya is Director of Worldwide Foundry and IP Business Development at Silvaco. Prior to Silvaco, Ashish has held senior strategic marketing and program management roles at leading semiconductor and IP companies including Honeywell, Applied Materials, Efficient Solar Power Systems, TSMC, and Virage Logic. Ashish is the author of five patents and holds an MBA from Cornell University and an MS in electrical engineering from Michigan Technological University.<\/p>\n

WHO SHOULD ATTEND:<\/h3>\n
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Engineers, manager, and executives looking to design SoCs for HPC, data center, AI\/ML, high-speed networking, 5G, and IoT applications.<\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/section>\n<\/div>\n

When<\/strong>: October 13, 2020
\nWhere<\/strong>: Online
\nTime<\/strong>: 10:00am-10:30am – (PST)
\nLanguage<\/strong>: English<\/p>\n

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Register!<\/h1>\n