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In this webinar you will learn about modeling approaches and methods related to Flat Panel Display applications using Silvaco\u2019s Utmost IV modeling software. Topics covered include; modeling of TFT devices, with emphasis on issues such as the frequency dispersion effect, SPICE modeling approaches for OLED devices, including Verilog-A models and macromodels. The webinar will also cover how to deal with devices and phenomena for which compact SPICE models may not be available. These aspects will be illustrated through several examples based on TCAD-generated data.<\/p>\n
![\"Dr.](\"\/wp-content\/uploads\/2020\/03\/bogdan.jpg\")
Dr. Bogdan Tudor is head of Silvaco\u2019s Device Characterization Group. He is responsible for all aspects of the Device Characterization Group\u2019s activities, including R&D, field operations, and modeling services. He has 15+ year experience in EDA and SPICE modeling fields with extensive expertise in device characterization, Compact Model development, MOSFET Aging Reliability Analysis, and software development. Dr. Tudor holds a M.Sc. in Electrical Engineering and a Ph.D. in Microelectronics from the Polytechnic University in Bucharest, Romania.<\/p>\n
When<\/strong>: May 14, 2020 Engineers, management, and academics who are interested in SPICE modeling methodologies for Display, TFT and OLED. Process and device design engineers, R&D management looking for simulation tools to investigate a wide material and device design space for OLEDs.<\/p>\n","protected":false},"excerpt":{"rendered":" May 14th 2020 | 10:00 am \u2013 10:30 am (PDT)<\/b>
\nWhere<\/strong>: Online
\nTime<\/strong>: 10:00am-11:00am – (PST)
\nLanguage<\/strong>: English<\/p>\nWHO SHOULD ATTEND:<\/h3>\n
\nIn this webinar you will learn about SPICE modeling approaches and methods related to flat panel display applications using Silvaco\u2019s Utmost IV modeling software. Topics covered include modeling of TFT devices, with emphasis on issues such as the frequency dispersion effect, and modeling of OLED devices, including the use of Verilog-A models and macromodels.<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7730],"tags":[],"class_list":["post-35802","post","type-post","status-publish","format-standard","hentry","category-modeling-webinars-zh-hans","entry"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/35802","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/comments?post=35802"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/35802\/revisions"}],"predecessor-version":[{"id":35807,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/35802\/revisions\/35807"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media?parent=35802"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/categories?post=35802"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/tags?post=35802"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}