www.ieee.org<\/a>.<\/p>\nGuido Notermans, Olivier Quittard, Anco Heringa, \u017deljko Mr\u010darica, Fabrice Blanc, Hans van Zwol, Theo Smedes, Thomas Keller, Peter de Jong,
\n“ESD robust high-voltage active clamps”,
\nMicroelectronics Reliability, Vol. 49, Issue 12, December 2009, pp. 1433-1439.<\/p>\n
J.A. Salcedo, J.J Liou, Z. Liu, J.E. Vinson TCAD,
\n“Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications”,
\nIEEE Transactions on Electron Devices, Vol. 54, issue 4, April 2007, pp. 822-832.<\/p>\n
G. Notermans, O. Quittard, A. Heringa, Z. Mrcarica, F. Blanc, H. van Zwol, T. Smedes, T Keller, and P. de Jong,
\n“Designing HV active clamps for HBM robustness”,
\n29th Electrical Overstress\/Electrostatic Discharge Symposium (EOS\/ESD), Sept. 2007, pp. 1B.1-1 – 1B.1-6.<\/p>\n
Changkun Park, Seok-Oh Yun, Jeonghu Han, Sang-Hoon Cheon, Jae-Woo Park, and Songcheol Hong,
\n“ESD characteristics of GaAs versus silicon diode”,
\nGallium Arsenide and Other Semiconductor Application Symposium (EGAAS 2005), Oct. 2005, pp. 273 – 276.<\/p>\n
J. A. Salcedo, J. J. Liou, J. C. Bernier,
\n“Design and integration of novel SCR-based devices for ESD protection in CMOS\/BiCMOS technologies”
\nIEEE Transactions on Electron Devices, Vol. 52, Issue 12, December 2005, pp. 2682-2689.<\/p>\n
Z. Zhu, Y. Hao,
\n“Characterization simulation of a deep sub-micron GGNMOSFET under TLP stress”
\nPan Tao Ti Hsueh Pao\/Chinese Journal of Semiconductors, Vol. 26, Issue 10, October 2005, pp. 196.<\/p>\n
J.-Y. Choi,
\n“AC modeling of the ggNMOS ESD protection device”
\nETRI Journal, Vol. 27, Issue 5, October 2005, pp. 628-634.<\/p>\n
J. -Y. Choi, W. S. Yang, D. Kim, Y. Kim,
\n“Thyristor input-protection device suitable for CMOS RF IC’s”
\nAnalog Integrated Circuits and Signal Processing, Vol. 43, Issue 1, April 2005, pp. 5-14.<\/p>\n
J. J. Liou and X. Gao,
\n“Design and modeling of on-chip electrostatic discharge (ESD) protection structures”
\nProceedings of the International Conference on Microelectronics, Vol. 24 II, 2004, pp. 619-624.<\/p>\n
A. A. Salman, R. Gauthier, C. Putnam, P. Riess, M. Muhammad, M. Woo, D. E. Ioannou,
\n“ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-”
\nIEEE Transactions on Device and Materials Reliability, Vol. 3, Issue 3, September 2003, pp. 79.<\/p>\n
X. Gao, J. J. Liou, W. Wong, S. Vishwanathan,
\n“An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance”
\nSolid-State Electronics, Vol. 47, June 2003, pp. 1105-1110.<\/p>\n
X. Gao, J. J. Liou, J. Bernier, G. Croft, W. Wong, S. Vishwanathan,
\n“Optimization of on-chip ESD protection structures for minimal parasitic capacitance”
\nMicroelectronics Reliability, Vol. 43, May 2003, pp. 725-733.<\/p>\n
A. Guilhaume, P. Galy, J. P. Chante, B. Foucher, S. Bardy, F. Blanc,
\n“ESD evaluation of a low voltage triggering SCR (LVTSCR) device submitted to transmission line pulse (TLP) test”
\nJournal of Electrostatics, Vol. 56, October 2002, pp. 281-294.<\/p>\n
A. Salman, R. Gauthier, E. Wu, P. Riess, C. Putnam, M. Muhammad, M. Woo, D. Ioannou,
\n“Electrostatic discharge induced oxide breakdown characterization in a 0.1”
\nAnnual Proceedings – Reliability Physics (Symposium), 2002, pp. 170-174.<\/p>\n
Gianluca Boselli, Stan Meeuwsen, Ton Mouthaan and Fred Kuper,
\n“Investigations on double-diffused MOS transistors under ESD zap conditions”
\nMicroelectronics Reliability, Vol. 41, Issue 3, March 2001, pp. 395-405.<\/p>\n
A. Guilhaume et al,
\n“Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges”
\nESREF 2001, pp. 1433-1437.<\/p>\n
J. C. Lee, A. Hoque, G. D. Croft, J. J. Liou, R. Young and J. C. Bernier,
\n“An electrostatic discharge failure mechanism in semiconductor devices, with applications to electrostatic discharge measurements using transmission line pulsing technique”
\nSolid-State Electronics, Vol. 44, Issue 10, 1 October 2000, pp. 1771-1781.<\/p>\n
Kevin Palser, Ann Concannon, Ray Duffy and Alan Mathewson,
\n“Analysis of external latch-up protection test structure design using numerical simulation”
\nMicroelectronics and Reliability, Vol. 39, Issue 5, May 1999, pp. 647-659.<\/p>\n
Kyuhyung Kwon et al,
\n“A Novel ESD Protection Technique for Submicron CMOS\/BiCMOS Technologies”
\nProc. EOS\/ESD Symposium, 1995, pp. 21-26.<\/p>\n
Freydin, Strachan,
\n“Simulation of Electrothermal Interactions in ESD Protection Devices”
\nIn-house paper, 1994.<\/p>\n
Hellstrom, Freydin, Velmre, Uda,
\n“Numerical Simulation of Electrothermal Effects in ESD Protection Devices”
\nESREF, 1992.<\/p>\n
Freydin, Velmre, Udal,
\n“Numerical Simulation of Electrothermal Interactions in Semiconductor Devices Experiencing ESD Pulses”
\nPro. Int Workshop on Computational Electronics.<\/p>\n","protected":false},"excerpt":{"rendered":"
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