My first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second DRAM was using only a 5V supply. Today we see SOCs running under a 1V supply voltage, but there is a totally different market for\u00a0power devices<\/strong>\u00a0that are at the other end of the voltage spectrum and they handle switching ranges from 12V \u2013 250V. To learn more about power devices and how the process and device modeling is done, I read a\u00a0Silvaco<\/strong>\u00a0publication entitled\u00a0Advanced Process and Device 3D TCAD Simulation of Split-Gate Trench UMOSFET<\/em><\/a>.<\/p>\n For vertical discrete power MOSFETs there are two important specifications that engineers look at:<\/p>\n A couple of approaches have been used for power devices: Trench MOSFETs, RSO MOSFETs. The winning approach has been the Split-Gate RSO MOSFETs because of their low channel resistance, plus ultra-low drift region resistance with a smaller Cgd (gate-to-drain capacitance), improving switching speeds. Process engineers use 3D TCAD tools to model power devices and optimize them by looking at the predicted values of:<\/p>\n Silvaco provides\u00a0Victory Process\u00a0and\u00a0Victory Device\u00a0simulators to do this modeling of power devices. So let\u2019s start with a 3D process simulation of a Split-Gate UMOSFET, where Victory Process is used to build the device structure. Several simulated process steps\u00a0 are shown below: A 3D numerical mesh is the next step using the\u00a0<\/span>Victory Mesh\u00a0tool, and a 3D Delaunay mesh was generated to accurately resolve the 3D geometrical features. Here\u2019s the result of meshing:<\/span><\/p>\n 3D device simulations are then run with the Victory Device simulator, and this is quite powerful because it can model 3D unstructured tetrahedral meshes for any device shape. To run Victor Device simulations you have several actions:<\/p>\n An initial solution is computed, then Id-Vg curves are produced for each Vds voltage, then transconductance gm-Vg are computed as shown below:<\/p>\n Here\u2019s the plot of Id-Vd at a select Vgs bias voltage:<\/span><\/p>\n A plot of Breakdown I-V is shown where the gate bias Vg = 0V:<\/span><\/p>\n Each of these I-V curves was generated by the\u00a0TonyPlot\u00a0tool.<\/p>\n C-V plots are simulated with Victory Device, and here\u2019s the small-signal (AC) results showing intrinsic capacitances:<\/p>\n Summary<\/strong><\/p>\n Process engineers equipped with the proper modeling and simulation tools can now predict the behavior of power devices like Split-Gate Resurf Stepped Oxide (SG-RSO) MOSFET. Instead of running lots of silicon, measuring, tweaking and repeating, engineers can accurately model and optimize virtually, saving lots of time and money. Read the\u00a0complete article online<\/a>.<\/p>\n\n
\n
\na) Formation of a deep trench with rounded bottom, both dry and wet etch steps
\nb) Shield oxide growth
\nc) Shield poly deposition
\nd) Inter-poly oxide deposition and etch back
\ne) Gate poly deposition and etch back
\nf) Core contact etching and deposition of the contact plug<\/p>\n![\"\"](\"\/wp-content\/uploads\/2020\/04\/Blog15.jpg\")
![\"\"](\"\/wp-content\/uploads\/2020\/04\/Blog16.jpg\")
\n
![\"\"](\"\/wp-content\/uploads\/2020\/04\/Blog17.jpg\")
![\"\"](\"\/wp-content\/uploads\/2020\/04\/Blog18.jpg\")
![\"\"](\"\/wp-content\/uploads\/2020\/04\/Blog19.jpg\")
![\"\"](\"\/wp-content\/uploads\/2020\/04\/Blog20.jpg\")