{"id":36074,"date":"2017-09-12T16:24:35","date_gmt":"2017-09-12T16:24:35","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/getting-to-know-the-new-mipi-alliance-i3csm-standard\/"},"modified":"2021-10-13T09:48:38","modified_gmt":"2021-10-13T16:48:38","slug":"getting-to-know-the-new-mipi-alliance-i3csm-standard","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/getting-to-know-the-new-mipi-alliance-i3csm-standard\/","title":{"rendered":"Getting to Know the New MIPI Alliance I3C Standard"},"content":{"rendered":"

\"Banner<\/p>\n

Getting to Know the New MIPI Alliance I3CSM<\/sup>\u00a0Standard<\/h1>\n

Mobile devices today contain a rich assortment of sensors that need to communicate their information as quickly as possible at the lowest possible power. To achieve this the MIPI Alliance has gathered industry leaders to create a new interface standard around connecting sensors.<\/p>\n

I3C is a new standard that has advantages in reducing pin count, increasing performance, and decreasing power while achieving some level of backwards compatibility with the long established I2C interface.<\/p>\n

What attendees will learn:<\/h2>\n
    \n
  • Background on the development of I3C<\/li>\n
  • Basic MIPI I3C signaling and protocol<\/li>\n
  • Comparison of I2C vs I3C<\/li>\n
  • Key features of I3C\n
      \n
    • Lower power<\/li>\n
    • Hot pluggable<\/li>\n
    • High Data Rate (HDR) modes<\/li>\n
    • Dynamic Addressing<\/li>\n
    • In-band- Interrupts<\/li>\n
    • Common Command Codes (CCC\u2019s)<\/li>\n<\/ul>\n<\/li>\n
    • I3C roadmap features<\/li>\n
    • Integrating I3C cores<\/li>\n<\/ul>\n

      Presenter<\/h2>\n

      \"\"Paul Kimelman has been designing and architecting ASIC, boards, and software for 35 years. He holds two Bachelors from University of California at Santa Cruz, one in Computer and Information Sciences, and one in Physiological Psychology. He currently is Platform Architect for Automotive Microcontrollers and Processors at NXP Semiconductors, and before that Senior Director of MCU Architecture at NXP, and was previously a Senior Architect at Texas Instruments, and before that at ARM.<\/p>\n

      Paul has spent most of his career focus on MCUs and deeply embedded systems. Since his architecting of ARM ARMv7-M (Cortex-M), he has focused on Cortex-M based MCUs. He has been an active contributor to the MIPI I3C specification, winning the 2016 Leadership award.<\/p>\n

      \"\"Warren Savage serves as the General Manager of the IP Division at Silvaco. He has spent his entire career in Silicon Valley with engineering and management roles in leading companies including Fairchild Semiconductor, Tandem Computers, Synopsys, and most recently with IPextreme which he founded in 2004 and was acquired by Silvaco in June 2016.<\/p>\n

      Warren holds a BS in Computer Engineering from Santa Clara University, an MBA from Pepperdine University and is the author\/co-author of three patents.<\/p>\n

      When<\/strong>: September 12, 2017
      \nWhere<\/strong>: Online
      \nTime<\/strong>: 10:00am-11:00am-(PST)
      \nLanguage<\/strong>: English<\/p>\n

      WHO SHOULD ATTEND:<\/h3>\n
      \n
      \n

      Chip architects, engineers, and product managers who are considering incorporating I3C into their next generation products.<\/p>\n<\/div>\n<\/div>\n

      \n