{"id":36577,"date":"2004-07-01T00:10:37","date_gmt":"2004-07-01T00:10:37","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/silvacos-rfic-design-suite\/"},"modified":"2021-10-13T10:36:40","modified_gmt":"2021-10-13T17:36:40","slug":"silvacos-rfic-design-suite","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/silvacos-rfic-design-suite\/","title":{"rendered":"Silvaco\u2019s RFIC Design Suite"},"content":{"rendered":"<h1>Silvaco\u2019s RFIC Design Suite<\/h1>\n<p class=\"feature\"><strong>Introduction<\/strong><\/p>\n<p>This article focuses on the use of Silvaco\u2019s RFIC Design Suite including PDK,\u00a0<em><strong>SmartSpice-RF<\/strong><\/em>, and\u00a0<strong><em>Gateway<\/em><\/strong>.<\/p>\n<p>Silvaco Process Design Kits (PDKs) have been developed to help start the analog and mixed signal design cycles. The design kit supplies you with all the foundry process specific models, symbols, simulation setup for the Silvaco set of design tools.<\/p>\n<p><em><strong>SmartSpice-RF<\/strong><\/em>\u00a0Harmonic Balance based Simulator provides a complete set of steady-state analyses and measurements to design GHz range RF wireless application ICs. It accurately and efficiently simulates noise, gain compression, harmonic distortion, oscillator phase noise, and intermodulation products in non-linear circuits using SPICE netlists.<\/p>\n<p><strong><em>Gateway<\/em><\/strong>\u00a0is the schematic entry for the Analog\/Mixed Signal\/RF Design design environment. The\u00a0<strong><em>Gateway<\/em><\/strong>\u00a0schematic is netlisted for\u00a0<em><strong>SmartSpice-RF<\/strong><\/em>\u00a0and tightly integrated for running simulations concurrent with the schematic.<\/p>\n<p>This article shows the basic steps needed to take a design from schematic entry to simulation using the TSMC 018 MM\/RF process and a set of Silvaco tools. These steps can be broken down into the following tasks.<\/p>\n<ul>\n<li class=\"regular\">Set up\u00a0<strong><em>Gateway<\/em><\/strong>\u00a0with the TSMC 018 MM\/RF schematic files to load an example circuit. The example here is the Low Noise Amplifier (LNA) Circuit<\/li>\n<\/ul>\n<ul>\n<li class=\"regular\">Perform the circuit simulation from the\u00a0<strong><em>Gateway<\/em><\/strong>\u00a0Schematic Window. Before you perform a simulation, include the TSMC_cm018 model library from TSMC into the netlist. The LNA circuit is simulated and waveforms are displayed within\u00a0<strong><em>SmartView<\/em><\/strong><\/li>\n<\/ul>\n<p class=\"feature\"><strong>How to Run SmartSpice-RF in Gateway<\/strong><\/p>\n<p>To use the environment for schematic, simulation, and post-processing, the following licenses are required:<\/p>\n<ul>\n<li class=\"regular\"><em><strong>Gateway<\/strong><\/em><\/li>\n<li class=\"regular\"><em><strong>SmartSpice -RF<\/strong><\/em><\/li>\n<li class=\"regular\"><em><strong>SmartView<\/strong><\/em><\/li>\n<\/ul>\n<p>The following example is for an LNA simulation using\u00a0<strong><em>SmartSpice-RF<\/em><\/strong>:<\/p>\n<ol>\n<li><span class=\"regular\">To create a schematic in Gateway, first load one or more schematic symbol libraries. The example circuit that we\u2019ve designed, the LNA Circuit, uses two different symbol libraries: spicelib and TSMC_cm018. The TSMC_cm018 kit symbol library contains process dependent symbols. spicelib (Silvaco\u2019s library) contains basic schematic symbols for example, pins, and grounds.<\/span><\/li>\n<\/ol>\n<p><img loading=\"lazy\" width=\"600\" height=\"800\" src=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_jul_2004_a1-e1611194302984.jpg\" class=\"cleaned-enfold-image\" alt=\"\" decoding=\"async\" loading=\"lazy\" \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This article focuses on the use of Silvaco\u2019s RFIC Design Suite including PDK,\u00a0SmartSpice-RF, and\u00a0Gateway.<\/p>\n","protected":false},"author":3,"featured_media":21979,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7723],"tags":[],"class_list":["post-36577","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard-zh-hans","entry","has-media"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36577","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/comments?post=36577"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36577\/revisions"}],"predecessor-version":[{"id":36582,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36577\/revisions\/36582"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media\/21979"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media?parent=36577"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/categories?post=36577"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/tags?post=36577"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}