\nThe Input\/output Buffer Information Specifi cation (IBIS) is a standard for electronic behavioral models based on I\/V and V\/T curve data. It is being developed by the IBIS Open Forum, which is affi liated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power\/ground bounce, transmission lines…) on printed circuit boards (PCBs).<\/p>\n
The IBIS standard offers a way to provide fast and accurate models of I\/O buffers without divulgating any proprietary technology process. As it protects IP, it is now widely used by semiconductor vendors as a replacement for SPICE netlists. The IBIS standard specifi es only what kind of information is provided, how this information is presented in ASCII fi les and how some data are derived from measurements or simulations. How these data are used and processed by a simulator is not part of the standard. The purpose of this documentation is to present the IBIS model support in SmartSpice<\/strong>.<\/p>\n The reader who is not familiar with the IBIS standard or would like to learn more about IBIS may refer to the Web site of the IBIS Open Forum at \u201chttp:\/\/www.eigroup.org\/ibis\u201d where numerous documents are available for download, including introductions, slide shows, articles and complete specifi cations (from the initial v1.0 to the latest v4.1 of January 2004).<\/p>\n 2. IBIS Buffer Equivalent Circuit Expert\u00a0Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of rectangles. Pwire objects enable extremely quick and efficient creation and editing of guard rings and shielded paths which are increasingly important due to higher integration density of IC designs.<\/p>\n","protected":false},"author":3,"featured_media":21571,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7723],"tags":[],"class_list":["post-36602","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard-zh-hans","entry","has-media"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36602","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/comments?post=36602"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36602\/revisions"}],"predecessor-version":[{"id":36607,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36602\/revisions\/36607"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media\/21571"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media?parent=36602"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/categories?post=36602"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/tags?post=36602"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nA buffer is implemented as a new element in SmartSpice. Even though different types of buffers are available to cover a wide range of functions and technologies, they are all base on the same equivalent circuit, which is shown on Figure 1.<\/p>\n![\"\"](\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_2004_a1.jpg\")
<\/p>\n","protected":false},"excerpt":{"rendered":"