{"id":36991,"date":"1999-04-02T17:04:28","date_gmt":"1999-04-02T17:04:28","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/mixed-signal-simulation-with-smartspice-in-the-cadence-design-framework-ii\/"},"modified":"2021-10-13T10:54:03","modified_gmt":"2021-10-13T17:54:03","slug":"mixed-signal-simulation-with-smartspice-in-the-cadence-design-framework-ii","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/mixed-signal-simulation-with-smartspice-in-the-cadence-design-framework-ii\/","title":{"rendered":"Mixed-Signal Simulation with SmartSpice in the Cadence Design Framework II"},"content":{"rendered":"<h1>Mixed-Signal Simulation with\u00a0<i>SmartSpice<\/i>\u00a0in the Cadence Design Framework II<\/h1>\n<p>Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between\u00a0<strong><em>SmartSpice<\/em><\/strong>\u00a0and the Analog Artist Electrical Design System and Composer Design Entry tools. This integration is achieved via the Cadence Spice Socket (cdsSpice) and the Open Analog Simulation Integration Socket (OASIS). It has been comprehensively documented in previous issues of the\u00a0<i>Simulation Standard<\/i>, and also in a new application note (Ref No. SS\/99-2).<\/p>\n<p>The\u00a0<b><i>SmartSpice<\/i><\/b>\u00a0Interface to DFII already supports automatic netlisting, cross-probing, back-annotation and many other standard features of the DFII simulation environment. In a significant upgrade, the latest release also allows the user to make\u00a0<b><i>SmartSpice<\/i><\/b>\u00a0the analog component of their DFII mixed-signal design and simulation environment, with Cadence Verilog-XL supplying the digital simulation capability. The additional integration code is distributed in the form of a mixed-mode context file. A context file is compiled SKILL code, which is installed into the Cadence installation hierarchy along with the pre-existing analog context file, and many other related files, with the command:<\/p>\n<p><img loading=\"lazy\" width=\"1281\" height=\"1669\" src=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2.jpg\" class=\"cleaned-enfold-image\" alt=\"\" decoding=\"async\" loading=\"lazy\" srcset=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2.jpg 1281w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-230x300.jpg 230w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-791x1030.jpg 791w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-768x1001.jpg 768w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-1179x1536.jpg 1179w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-1151x1500.jpg 1151w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-541x705.jpg 541w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-28x37.jpg 28w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-42x55.jpg 42w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_apr_1999_a2-37x48.jpg 37w\" sizes=\"auto, (max-width: 1281px) 100vw, 1281px\" \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between\u00a0SmartSpice\u00a0and the Analog Artist Electrical Design System and Composer Design Entry tools. This integration is achieved via the Cadence Spice Socket (cdsSpice) and the Open Analog Simulation Integration Socket (OASIS). It has been comprehensively documented in previous issues of the\u00a0Simulation Standard, and also in a new application note (Ref No. SS\/99-2).<\/p>\n","protected":false},"author":5,"featured_media":21505,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7723],"tags":[],"class_list":["post-36991","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard-zh-hans","entry","has-media"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36991","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/comments?post=36991"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36991\/revisions"}],"predecessor-version":[{"id":36996,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/36991\/revisions\/36996"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media\/21505"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media?parent=36991"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/categories?post=36991"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/tags?post=36991"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}