{"id":37089,"date":"1998-04-02T16:12:04","date_gmt":"1998-04-02T16:12:04","guid":{"rendered":"https:\/\/silvaco-stage.betagentechnologies.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/atlas-mixedmode-simulation-of-a-three-stage-cmos-ring-oscillator-part-i-mixedmode-setup\/"},"modified":"2021-10-13T10:57:16","modified_gmt":"2021-10-13T17:57:16","slug":"atlas-mixedmode-simulation-of-a-three-stage-cmos-ring-oscillator-part-i-mixedmode-setup","status":"publish","type":"post","link":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/atlas-mixedmode-simulation-of-a-three-stage-cmos-ring-oscillator-part-i-mixedmode-setup\/","title":{"rendered":"ATLAS\/MixedMode Simulation of a Three Stage CMOS Ring Oscillator Part I: MixedMode Setup"},"content":{"rendered":"<h1><strong>ATLAS\/MixedMode Simulation of a Three Stage CMOS Ring Oscillator<\/strong><br \/>\n<i>Part I: MixedMode Setup<\/i><\/h1>\n<p class=\"feature\">Introduction<\/p>\n<p>Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One of the most useful results obtainable from a ring oscillator test structure is the delay time per gate. This information is especially important for successful design of high speed clock circuits, such as Phase Locked Loops (PLL&#8217;s) and Voltage Controlled Oscillators (VCO&#8217;s).<\/p>\n<p>This article is aimed at demonstrating the simulation of a three stage CMOS ring oscillator. Using\u00a0<b>ATLAS\/MixedMode<\/b>, MOSFET devices in the circuit are simulated numerically. For Part I, both NMOS and PMOS devices were created with analytical doping profiles using\u00a0<b>ATLAS<\/b>. In Part II these devices will be created from process simulation using\u00a0<b>ATHENA<\/b>\u00a0and process variations will be analyzed.\u00a0<i>Part II will be published in the next issue of the Simulation Standard.<\/i><\/p>\n<p><img loading=\"lazy\" width=\"1210\" height=\"1669\" src=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2.jpg\" class=\"cleaned-enfold-image\" alt=\"\" decoding=\"async\" loading=\"lazy\" srcset=\"https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2.jpg 1210w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-217x300.jpg 217w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-747x1030.jpg 747w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-768x1059.jpg 768w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-1114x1536.jpg 1114w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-1087x1500.jpg 1087w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-511x705.jpg 511w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-27x37.jpg 27w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-40x55.jpg 40w, https:\/\/silvaco-stage.betagentechnologies.com\/wp-content\/uploads\/simulationstandard\/simstd_may_1998_a2-35x48.jpg 35w\" sizes=\"auto, (max-width: 1210px) 100vw, 1210px\" \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One of the most useful results obtainable from a ring oscillator test structure is the delay time per gate.<\/p>\n","protected":false},"author":5,"featured_media":22174,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7723],"tags":[],"class_list":["post-37089","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard-zh-hans","entry","has-media"],"_links":{"self":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/37089","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/comments?post=37089"}],"version-history":[{"count":1,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/37089\/revisions"}],"predecessor-version":[{"id":37093,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/posts\/37089\/revisions\/37093"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media\/22174"}],"wp:attachment":[{"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/media?parent=37089"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/categories?post=37089"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/silvaco-stage.betagentechnologies.com\/zh-hans\/wp-json\/wp\/v2\/tags?post=37089"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}